1. Field of the Invention
The present invention generally relates to digital electronic circuitry and more particularly relates to digital electronic circuitry for generating precise time delays.
2. Description of the Prior Art
It is well known that electronic circuits exhibit propagation time delays and such delays may be useful for various applications. U.S. Pat. No. 4,684,897, issued to Richards et al., shows the use of an electronic delay circuit, often called a "delay line", to produce predetermined frequency shifts in a signal. Distance is measured using delay circuits in U.S. Pat. No. 4,055,830, issued to Wilson et al. Other applications for electronic delay lines include: analog-to-digital conversion in U.S. Pat. No. 3,701,148, issued to Frei; measurement of signal slope in U.S. Pat. No. 4,815,113, issued to Ludwig et al.; calibration of oscilloscopes in U.S. Pat. No. 3,656,053, issued to Richman; reformation of a distorted pulse train using a comparison of two delay line outputs in U.S. Pat. No. 5,054,038, issued to Hedberg; and fluid flow measurement in U.S. Pat. No. 4,120,032, issued to Mirdadian.
Whereas most earlier prior art devices utilized analog delay circuitry, the current trend is to employ digital circuits whenever feasible as a means of controlling costs of manufacture and use. At times this involves digital control of delay circuits as shown in U.S. Pat. No. 3,681,706, issued to Harzer.
Even though circuit delays are important to many applications, it is also known that digital circuit propagation delays tend to vary with temperature, input signal, and supply voltage. To minimize and/or control this variability, a number of techniques are employed. U.S. Pat. No. 4,383,216, issued to Dorier et al., is concerned with chip-to-chip variation and attempts to control this with an on-chip delay voltage regulator. Iwahashi et al., in U.S. Pat. No. 4,473,762, attempt temperature compensation in MOS circuits with voltage control. CMOS output buffer switching time control is implemented in U.S. Pat. No. 4,818,901, issued to Young et al., by changing from constant current to constant voltage mode during the switching operation. A voltage controlled oscillator is employed by Bell et al. in U.S. Pat. No. 4,494,021, to minimize variation in delay line timing.
A highly effective solution to delay line timing control is found in U.S. Pat. No. 4,623,805, issued to Flora et al. This technique uses feedback supplied by phase comparison of the multi-tap delay line output to a fixed delay to provide for selection of the appropriate delay line tap. The bias voltage is varied in U.S. Pat. No. 4,641,048, issued to Pollock, to provide a measure of control over ECL circuit propagation delays.
U.S. Pat. No. 4,939,389, issued to Cox et al., uses a string of gates on a monolithic device to measure the propagation delay of the functionally active circuits on that device. In that way, it is assumed that compensation may be made for variations in propagation delays. U.S. Pat. No. 4,591,124, issued to Ledzius et al., provides a clock circuit directly on the monolithic device in an attempt to clock the device at or near the maximum rate under ambient conditions.
An active delay line using digital circuitry is found in U.S. Pat. No. 4,889,071, issued to Morales. In this approach, a reference clock output is compared to the outputs of the various delay elements. Phase differences result in changes in the control voltage supplied to the corresponding delay elements. In this manner, it is deemed that the individual delay elements can be held to have a constant propagation delay.
Though there are many applications known in the prior art for both analog and digital delay lines, most designs encounter change in delay time as a function of temperature, supply voltage, and other ambient variations. The standard technique for dealing with these variations in digital circuity is to measure phase change using some external standard and providing compensation by changes in voltage or mode in an attempt to maintain constant individual delay element propagation delays. This technique tends to be quite costly in view of the added hardware and need to maintain an accurate external timing standard.